The present invention relates to an integrated circuit (IC), and more particularly to a system and method for protecting a vulnerable device within an IC from damage due to an electrostatic discharge (ESD).
IC manufacturing technology is continually improving. Advances in IC manufacturing technology have led to many improvements, including the ability to form smaller devices within an IC. In turn, this has resulted in the ability to fit more devices within a smaller sized chip. Unfortunately, these advances have also led to new problems. One of these problems is that the reduced device size decreases the ability of some devices to withstand an ESD event.
When an ESD event occurs on an external pad of an IC, it causes a large voltage spike to appear across some of the devices within the IC. If this sudden voltage spike is large enough, an internal device may experience a condition known as avalanche breakdown. When avalanche breakdown occurs, the device undergoes a snapback to a low holding voltage and large currents can flow through the device. These currents may become large enough to raise the device junction temperatures high enough to melt silicon, thus damaging or destroying the device. The voltage at which avalanche breakdown occurs across a device is known as the device's breakdown voltage.
Some devices, such as transistors, have multiple breakdown voltages depending on which junction the voltage is applied across, or whether the voltage is positive or negative. In addition, the current state of the device can have an effect on the magnitude of the breakdown voltage. For example, whether a transistor's base is open or shorted to the emitter can change the collector-emitter breakdown voltage of the transistor.
One method of protecting a vulnerable device from an ESD event is by increasing the size of the device. By increasing the size, the current carrying ability is increased, causing an increased tolerance to ESD events. However, this is often undesirable because an increased device size leads to an increase in the overall chip size.
Another method of protecting a device from an ESD event is to place an ESD clamp in parallel with the vulnerable device from the external pad to ground. An ESD clamp ensures that the voltage on the pad does not exceed the breakdown voltage of the device being protected. When the voltage across the device nears the breakdown voltage, the ESD clamp turns on and allows the ESD current to bypass the device. However, it is often undesirable to place an ESD clamp on an external pad because the ESD clamp adds an additional load to the pad, which is often undesirable during normal operation of the IC.
Another method used to protect a vulnerable device from an ESD event is to stack transistors in a cascode configuration. By stacking the transistors, the breakdown voltage is nearly doubled from that of a single transistor. Again, this configuration is beneficial during an ESD event but is often not desirable during normal operation of the IC.
Therefore, there is a need for a dynamic ESD protection system and method that would not interfere with the pad loading or normal operation of the IC, but would dynamically protect a vulnerable device from ESD without significantly increasing the overall size of the IC.